Index of ftp://wilbur.eng.auburn.edu/pub/elec7970

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[ ] BothChipsGDS  691.88Kb  August 2 2002
[TXT] Brad Creating The Layout Uing IC Station.doc  108.50Kb  August 1 2002
[TXT] Brad SCHEMATIC AND SYMBOL DESIGN USING DESIGN ARCHITECT.doc  82.50Kb  August 1 2002
[TXT] Brad Using Quicksim Pro To Simulate The Circuit With A VHDL Model.doc  167.50Kb  August 1 2002
[TXT] Brad Using Quicksim to Simulate the Model.doc  93.00Kb  August 1 2002
[TXT] CaiWangReport.doc  36.28Mb  July 30 2002
[TXT] EE7970_JinLi.doc  8.08Mb  August 1 2002
[ ] EE7970_KN.GDS  687.88Kb  August 1 2002
[TXT] HaihuaYan ADK Cell Design Process.doc  970.00Kb  August 1 2002
[TXT] HaihuaYan Design Rule Check.doc  430.00Kb  August 1 2002
[TXT] HaihuaYan Schematic Design Using Design Architect.doc  543.50Kb  August 1 2002
[TXT] HaihuaYan Some Problems.doc  21.00Kb  August 1 2002
[TXT] HaihuaYan Transient Simulation with Accusim.doc  894.00Kb  August 1 2002
[TXT] HaihuaYanDelay Analysis Using Quickpath.doc  447.50Kb  August 1 2002
[TXT] JinghongMaQiFengReport.doc  9.87Mb  August 1 2002
[TXT] LipingGuo.doc  1.60Mb  August 1 2002
[TXT] MentorTutorial_ygchen.doc  32.21Mb  July 30 2002
[TXT] Narayanan.doc  1.54Mb  August 1 2002
[TXT] QinghongYu1.doc  5.70Mb  August 2 2002
[TXT] QinghongYu2.doc  2.56Mb  August 2 2002
[TXT] QinghongYu3.doc  10.63Mb  August 2 2002
[TXT] QinghongYu4.doc  16.25Mb  August 2 2002
[TXT] S_Dalvi_J_Huang.doc  9.68Mb  August 1 2002
[TXT] YijingChenReport.doc  24.62Mb  July 30 2002
[ ] ee7970_chenyij.gds  684.98Kb  August 19 2002
[ ] ee7970_dillard.gds  785.44Kb  August 19 2002
[TXT] ee7970_kezwang.doc  2.05Mb  August 1 2002
[ ] ee7970_qh3.gds  671.29Kb  August 14 2002
[ ] ee7970_qh4.gds  671.29Kb  August 15 2002
[ ] ee7970_ramkumar.gds  657.36Kb  August 1 2002

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